Publications

Found 24 results
Author Title Type [ Year(Asc)]
Filters: Author is David Patterson  [Clear All Filters]
2022
Chasins, S., Cheung A., Crooks N., Ghodsi A., Goldberg K., Gonzalez J. E., et al. (2022).  The Sky Above the Clouds: A Berkeley View on the Future of Cloud Computing. arxiv.org.
2013
Beamer, S., Buluç A., Asanović K., & Patterson D. (2013).  Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search.
Cook, H., Moretó M., Bird S., Dao K., Patterson D., & Asanović K. (2013).  A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness.
2012
Beamer, S., Asanović K., & Patterson D. (2012).  Direction-Optimizing Breadth-First Search.
Haussler, D., Patterson D., Diekhans M., Fox A., Jordan M. I., Joseph A. D., et al. (2012).  A Million Cancer Genome Warehouse.
2011
Cook, H., Gonina E., Kamil S., Friedland G., Patterson D., & Fox A. (2011).  CUDA-Level Performance with Python-Level Productivity for Gaussian Mixture Model Applications.
Tan, Z., Asanović K., & Patterson D. (2011).  Datacenter-Scale Network Research on FPGAs.
Zaharia, M., Bolosky W. J., Curtis K., Fox A., Patterson D., Shenker S. J., et al. (2011).  Faster and More Accurate Sequence Alignment with SNAP.
Waterman, A., Lee Y., Patterson D., & Asanović K. (2011).  The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA.
Beamer, S., Asanović K., & Patterson D. (2011).  Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500.
2010
Tan, Z., Waterman A., Cook H., Bird S., Asanović K., & Patterson D. (2010).  A Case for FAME: FPGA Architecture Model Execution. 290-301.
Tan, Z., Asanović K., & Patterson D. (2010).  An FPGA-Based Simulator for Datacenter Networks.
Tan, Z., Waterman A., Avižienis R., Lee Y., Cook H., Patterson D., et al. (2010).  RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors.
2009
Shalf, J., Asanović K., Patterson D., Keutzer K., Mattson T.., & Yelick K. (2009).  The Manycore Revolution: Will HPC Lead or Follow?. 40-49.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
2008
Tan, Z., Asanović K., & Patterson D. (2008).  An FPGA Host-Multithreaded Functional Model for SPARC v8.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2008).  The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View.
2007
Wawrzynek, J., Patterson D., Oskin M., Lu S-L., Kozyrakis C., Hoe J. C., et al. (2007).  RAMP: Research Accelerator for Multiple Processors. IEEE Micro. 27(2), 46-57.
1996
Culler, D. E., Karp R. M., Patterson D., & Sahay A. (1996).  LogP: A Practical Model of Parallel Computation. Communications of the ACM. 39(11), 78-85.
1994
Hellerstein, L., Gibson G. A., Karp R. M., Katz R.. M., & Patterson D. (1994).  Coding techniques for handling failures in large disk arrays. Algorithmica. 12(2-3), 182-208.
1993
Culler, D. E., Karp R. M., Patterson D., Sahay A., Schauser K. Erik, Santos E. E., et al. (1993).  LogP: towards a realistic model of parallel computation. SIGPLAN Notices. 28,
Culler, D. E., Karp R. M., Patterson D., Sahay A., Schauser K. Erik, Santos E. E., et al. (1993).  LogP: towards a realistic model of parallel computation. Proceedings of the Fourth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. 1-12.
1989
Gibson, G. A., Hellerstein L., Karp R. M., Katz R. H., & Patterson D. (1989).  Failure correction techniques for large disk arrays. Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-III). 123-132.