Publications

Found 68 results
Author Title Type [ Year(Desc)]
Filters: Author is Krste Asanović  [Clear All Filters]
2008
Tan, Z., Asanović K., & Patterson D. (2008).  An FPGA Host-Multithreaded Functional Model for SPARC v8.
Lee, J. W., Ng A.., & Asanović K. (2008).  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. 89-100.
Krashinsky, R., Batten C., & Asanović K. (2008).  Implementing the Scale Vector-Thread Processor. ACM Transactions on Design Automation of Electronic Systems. 13(3), 
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2008).  The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View.
2009
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2009).  Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro. 29(4), 8-21.
Beamer, S., Asanović K., Batten C., Joshi A., & Stojanovic V. (2009).  Designing Multi-Socket Systems Using Silicon Photonics. 521-522.
Pan, H., Hindman B., & Asanović K. (2009).  Lithe: Enabling Efficient Composition of Parallel Libraries.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., & Asanović K. (2009).  Manycore Processor Networks with Monolithic Integrated CMOS Photonics.
Shalf, J., Asanović K., Patterson D., Keutzer K., Mattson T.., & Yelick K. (2009).  The Manycore Revolution: Will HPC Lead or Follow?. 40-49.
Jones, C.. G., Liu R., Meyerovich L.., Asanović K., & Bodik R. (2009).  Parallelizing the Web Browser.
Catanzaro, B., Kamil S., Lee Y., Asanović K., Demmel J., Keutzer K., et al. (2009).  SEJITS: Getting Poductivity AND Performance with Selective Embedded JIT Specialization.
Joshi, A., Batten C., Kwon Y-J., Beamer S., Shamim I., Asanović K., et al. (2009).  Silicon-Photonic Clos Networks for Global On-Chip Communication. 124-133.
Liu, R., Klues K., Bird S., Hofmeyr S., Asanović K., & Kubiatowicz J. D. (2009).  Tessellation: Space-Time Partitioning in a Manycore Client OS.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
2010
Tan, Z., Waterman A., Cook H., Bird S., Asanović K., & Patterson D. (2010).  A Case for FAME: FPGA Architecture Model Execution. 290-301.
Pan, H., Hindman B., & Asanović K. (2010).  Composing Parallel Software Efficiently with Lithe. 376-387.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., Beamer S., Chen S.., et al. (2010).  A Design-Space Exploration for CMOS Photonic Processor Networks.
Tan, Z., Asanović K., & Patterson D. (2010).  An FPGA-Based Simulator for Datacenter Networks.
Asanović, K., & Wittig R.. (2010).  Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California. IEEE Micro. 30(2), 5-6.
Tan, Z., Waterman A., Avižienis R., Lee Y., Cook H., Patterson D., et al. (2010).  RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors.
Beamer, S., Sun C.., Kwon Y-J., Joshi A., Batten C., Stojanovic V., et al. (2010).  Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics. 129-140.
Colmenares, J. A., Bird S., Cook H., Pearce P., Zhu D.., Shalf J., et al. (2010).  Resource Management in the Tessellation Manycore OS.
2011
Tan, Z., Asanović K., & Patterson D. (2011).  Datacenter-Scale Network Research on FPGAs.
Lee, Y., Avižienis R., Bishara A.., Xia R.., Lockhart D.., Batten C., et al. (2011).  Exploring the Tradeoffs Between Programmability and Efficiency in Data-Parallel Accelerators. 129-140.

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