Publications

Found 15 results
Author Title Type [ Year(Asc)]
Filters: Author is Christopher Batten  [Clear All Filters]
2013
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2013).  Designing Chip-Level Nanophotonic Interconnection Networks.
2012
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2012).  Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2012).  Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
2011
Lee, Y., Avižienis R., Bishara A.., Xia R.., Lockhart D.., Batten C., et al. (2011).  Exploring the Tradeoffs Between Programmability and Efficiency in Data-Parallel Accelerators. 129-140.
2010
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., Beamer S., Chen S.., et al. (2010).  A Design-Space Exploration for CMOS Photonic Processor Networks.
Beamer, S., Sun C.., Kwon Y-J., Joshi A., Batten C., Stojanovic V., et al. (2010).  Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics. 129-140.
2009
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2009).  Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro. 29(4), 8-21.
Beamer, S., Asanović K., Batten C., Joshi A., & Stojanovic V. (2009).  Designing Multi-Socket Systems Using Silicon Photonics. 521-522.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., & Asanović K. (2009).  Manycore Processor Networks with Monolithic Integrated CMOS Photonics.
Joshi, A., Batten C., Kwon Y-J., Beamer S., Shamim I., Asanović K., et al. (2009).  Silicon-Photonic Clos Networks for Global On-Chip Communication. 124-133.
2008
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2008).  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. 21-30.
Batten, C., Aoki H.., & Asanović K. (2008).  The Case for Malleable Stream Architectures.
Krashinsky, R., Batten C., & Asanović K. (2008).  Implementing the Scale Vector-Thread Processor. ACM Transactions on Design Automation of Electronic Systems. 13(3), 
2007
Batten, C., Krashinsky R., & Asanović K. (2007).  Scale Control Processor Test-chip.
Krashinsky, R., Batten C., & Asanović K. (2007).  The Scale Vector-Thread Processor.